Original Title: Vlsi DesignVHDL Modeling and Design Flow VLSI : Complete VLSI design flow (with reference to an EDA tool), Sequential, Data flow and structural modeling, Functions, Procedures, Attributes, Test benches, Synthesizable and non-synthesizable statements; Packages and configurations modeling in VHDL with examples of circuits such as counters, Shift registers, Bidirectional bus, etc. FSM and Sequential Logic Principles Sequential circuits, Meta-stability synchronization, Design of finite state machines and state minimization, FSM CASE STUDIES - Traffic light control, Lift control and UART, STA and DTA. Programmable Logic Devices The CPLDs, Study of architecture of CPLD and study of the architecture of FPGA.System On Chip One, Two phase clock, Clock distribution, Power distribution, Power optimization, SRC and DRC, Design validation, Global routing, Switch box routing, Off chip connections, I/O architectures, Wire parasitics, EMI immune design, Study of memory-Basics of memory includes types of memory cells and memory architectures, Types of memory based on architecture specific and application specific viz. SRAM, DRAM, SDRAM, FLASH, FIFO. CMOS VLSI CMOS parasitics, Equivalent circuit, Body effect, Technology scaling, parameter, Detail study of inverter characteristics, Power dissipation, Power delay product, CMOS combinational logic design and W/L calculations, Transmission gates, Introduction to CMOS layout. Testability Need of design for testability, Introduction to fault coverage, Testability, Design-for-Testability, Controllability and Observability, Stuck-at Fault Model, Stuck-Open and Stuck-Short faults, Boundary scan check, JTAG technology, TAP controller and TAP controller state diagram, Scan path, Full and Partial scan, BIST.